The ByoRISC configurable processor family

Customizable/extensible processors can be tuned to exploit applications of interest in modern platform-based design. However, in most cases they are implemented as extensions of legacy architectures, a policy that poses significant limitations to achieving high performance improvements. In this paper, the paradigm of the contemporary ByoRISC processor family is presented. The ByoRISC specification provides an extensive set of architectural parameters that can be applied to a baseline processor, that can be extended by application-specific hardware extensions (ASHEs) in the form of either custom instruction units or locally-interfaced coprocessors. Such ASHEs can implement multi-input multi-output (MIMO) computations with local state that may have an arbitrary number and combination of load/store accesses to the data memory. The performance characteristics of the proposed processors have been evaluated for both FPGA and ASIC implementations, proving that ByoRISC is a viable solution in present-day SoC design. A case study of an image processing pipeline is also presented to highlight the process of utilizing a ByoRISC-based custom processor.